The present invention relates to a control voltage generating circuit, a constant current source circuit, and a delay circuit and a logic circuit including the same.
Along with an increase in delay variation due to a low voltage design and difficulty in timing design of clock signals in a large-scale design, an increasing number of LSIs (Large Scale Integrations) are requiring compensation for a hold time by adding a large amount of delay to each logic cell. In order to compensate for the hold time by adding a large amount of delay, it is necessary to use a delay circuit for adding a delay to a signal, the hold time of which is to be compensated for. There have been known the following two methods using such a delay circuit. One is (1) a method of providing a number of delay circuits corresponding to the amount of required delay, and the other is (2) a method using a delay circuit, a drive current for which is controlled by a constant current source.
Techniques using a delay circuit, a drive current for which is controlled by a constant current source, are disclosed as described below.
Japanese Unexamined Patent Application Publication No. 05-268009 discloses a delay circuit including a plurality of COMS inverters including a current control type CMOS inverter; and a current mirror circuit for supplying a constant current to the current control type CMOS inverter.
Japanese Unexamined Patent Application Publication No. 2005-117442 discloses a delay circuit including a constant current source, a delay stage, and a compensation circuit. The delay stage determines an operating delay time of an output with respect to an input, depending on a constant current from the constant current source. The compensation circuit reversely compensates for a fluctuation of delay characteristics due to process variations of the delay stage, for example.
Japanese Unexamined Patent Application Publication No. 11-168362 discloses a delay circuit including constant voltage generating means and delay means. The constant voltage generating means absorbs a fluctuation of power supply voltage and generates a constant internal power supply voltage lower than the power supply voltage. The delay means includes a plurality of inverters which are driven by the internal power supply voltage and connected in cascade. The constant voltage generating means includes P-channel MOS transistors and N-channel MOS transistors mixed therein. Japanese Unexamined Patent Application Publication No. 2000-59184 also discloses a delay circuit including a voltage generating unit for supplying a constant voltage to a plurality of inverters connected in cascade.
Japanese Unexamined Patent Application Publication No. 09-270692 discloses a temperature compensation circuit including a temperature detection circuit and an inverter. The temperature detection circuit includes an active element (a MOS transistor) having a temperature dependence and a passive element (a resistor) having no temperature dependence. A drive current for the inverter is controlled based on detection results of the temperature detection circuit. Japanese Unexamined Patent Application Publication No. 2001-285036 also discloses a delay circuit including a control voltage generating unit including a MOS transistor and a resistor, and an inverter, a drive current for which is controlled based on output results of the control voltage generating unit.